1. Field of the Invention
The present invention relates to a flat panel display device, and more particularly, a liquid crystal display device with a built-in touch screen, which enhances driving performance, and reduces manufacturing costs by a simplified manufacturing process, and a method for manufacturing the same.
2. Discussion of the Related Art
Recent developments in various mobile electronic equipment such as mobile terminal and notebook computer has increased the demand for an applicable flat panel display device.
The flat panel display device may include a liquid crystal display device (LCD), a plasma display panel (PDP), a field emission display device (FED), a light-emitting diode display device (LED), and etc. Among the various flat panel display devices, the LCD device is widely used owing to various advantages, for example, technical development for mass production, ease of driving means, low power consumption, high-quality resolution, and large-sized screen.
Instead of using a related art mouse or keyboard used as an input device, a touch screen recently has been used as a new input device for the flat panel display device, wherein the touch screen enables a user to directly input information by the use of finger or pen.
The touch screen has been widely applied in various fields, for example, mobile terminals such as navigation, terminals for industrial use, notebook computer, automatic teller machine (ATM), mobile phone, MP3, PDA, PMP, PSP, mobile game machine, DMB receiver, and tablet PC; and electric appliances such as refrigerator, microwave oven, and washing machine. Furthermore, an easy operational method of the touch screen rapidly enlarges the application field.
Research and development of a slim flat panel display device, such as an LCD device with a built-in touch screen has occurred. Especially, an in-cell touch type LCD device has been most actively researched and developed, wherein the in-cell touch type LCD device refers to an LCD device which uses an element existing in the related art structure, for example, a common electrode on a lower substrate, as a touch-sensing electrode.
FIG. 1 illustrates an LCD device with a built-in touch screen according to the related art, and a method for driving the same.
Referring to FIG. 1, the LCD device with a built-in touch screen according to the related art comprises lower and upper substrates 50 and 60 bonded to each other with a liquid crystal layer (not shown) interposed therebetween.
On the upper substrate 60, there are a black matrix 62; red, green, and blue color filters 64R, 64G, and 64B; and an overcoat layer 66. In this case, the black matrix 62 defines a pixel region corresponding to each of plural pixels. Also, the red, green, and blue color filters 64R, 64G, and 64B are respectively formed in the respective pixel regions defined by the black matrix 62. The overcoat layer 66 covers the red, green, and blue color filters 64R, 64G, and 64B and the black matrix 62, to thereby planarize the upper substrate 60.
On the lower substrate 50, there is a pixel array 40 including plural pixels to drive the liquid crystal layer and detect a touching point by finger or pen.
Each of the plural pixels is defined by gate and data lines crossing each other. At the crossing portion of the gate and data lines, there is a thin film transistor (hereinafter, referred to as ‘TFT’). Each of the plural pixels includes a common electrode and a pixel electrode.
FIG. 2 is a cross section view illustrating a lower substrate in the LCD device with a built-in touch screen according to the related art. FIG. 2 shows a lower substrate in a fringe field switch (FFS) mode.
Referring to FIG. 2, each pixel of the lower substrate 50 is formed on a glass substrate. Each pixel includes a light-shielding layer 71 for preventing incident light; a buffer layer 51 on the light-shielding layer 71; an active layer 72 on the buffer layer 51; a gate insulating layer 52 on the active layer 72; and a gate electrode 73 of a metal material on the gate insulating layer 52, wherein the gate electrode 73 is partially overlapped with the active layer 72.
There are an interlayer dielectric (ILD) 53 and a data electrode 74. The interlayer dielectric 53 is formed on the gate electrode 73, to thereby insulate the gate electrode 73 from the data electrode 74. The data electrode 74 is electrically connected with the active layer 72, wherein the active layer 72 is partially exposed by a contact hole formed by etching the gate insulating layer 52 and the interlayer dielectric 53.
At this time, the data electrode 74 is formed by burying a metal material in the contact hole exposing some portions of the active layer 72. The data electrode 74 is electrically connected with a pixel electrode 77.
In each pixel of the lower substrate 50, there are a first passivation layer (PAS0) 54, a second passivation layer (PAS1) 55, and a common electrode 75 sequentially formed on the interlayer dielectric 53. The first and second passivation layers (PAS0, PAS1) 54 and 55 are formed to cover the gate electrode 71 and the data electrode 74. The common electrode 75 is formed on the second passivation layer 55, wherein the common electrode 75 is formed of a transparent conductive material such as Indium-Tin-Oxide (ITO).
In each pixel of the lower substrate 50, there are a conductive line (3rd metal) 76, a third passivation layer (PAS2) 56, and the pixel electrode 77. The conductive line 76 is formed on and electrically connected with a predetermined portion of the common electrode 75. The third passivation layer 56 is formed to cover the common electrode 75 and the conductive line 76. The pixel electrode 77 is electrically connected with an upper portion of the third passivation layer 56 and the data electrode 74, wherein the pixel electrode 77 is formed of a transparent conductive material.
The contact hole is formed by partially etching the first, second and third passivation layers (PAS0, PAS1, and PAS2) 54, 55 and 56. Through the contact hole, the upper portion of the data electrode 74 is exposed.
In this case, a predetermined portion of the second passivation layer (PAS1) 55, which is formed on the first passivation layer (PAS0) 54, is first etched, and then predetermined portions of the first and third passivation layers (PAS0, PAS2) 54 and 56 are etched at the same time, to thereby expose the upper portion of the gate electrode 74
The pixel electrode 77 is formed inside the contact hole formed by etching the first, second, and third passivation layers (PAS0, PAS1, PAS2) 54, 55 and 56, as well as on the third passivation layer 56. Thus, the pixel electrode 77 is electrically connected with the data electrode 74.
In the related art structure, the open region of the contact hole for the electric connection between the data electrode 74 and the pixel electrode 77 is determined depending on an etching area in the first, second and third passivation layers 54, 55 and 56. Especially, the open region of the contact hole for the electric connection between the data electrode 74 and the pixel electrode 77 is largely determined depending on the etching area of the second passivation layer 55.
Accordingly, the exposed region of the data electrode 74 is reduced so that a contact region between the data electrode 74 and the pixel electrode 77 is also reduced, to thereby deteriorate contact efficiency.
During photolithography for etching the third passivation layer 56 after the second passivation layer 55, there might be an alignment failure and a contact failure caused by foreign matters.
In the LCD device with a built-in touch screen according to the related art having the above structure, the common electrode 75 serves as a touch-sensing electrode for a non-display mode, thereby sensing a capacitance (Ctc) based on a user's touch, and detecting a touch point through the sensed capacitance.
The LCD device with a built-in touch screen according to the related art is formed in such a way that the common electrode 75 is arranged in each individual pixel, and the respective common electrodes 75 are electrically connected with each other by the use of conductive line 76.
Accordingly, the process of forming the common electrode 75 is separately carried out from the process of forming the conductive line 76, whereby the manufacturing cost is increased and the yield is deteriorated due to the complicated manufacturing process.
Amorphous silicon (a-Si) TFT has disadvantages of low driving speed, and limitation in design of fine line width. In order to overcome these disadvantages, the elements of the lower substrate 505 (for example, TFT) may be formed of low-temperature poly silicon (LTPS).
If the elements of the lower substrate 505 (for example, TFT) are formed of low-temperature poly silicon (LTPS), as shown in FIG. 3, the process inevitably uses 10 masks. Also, plural processes (for example, 155 steps) are carried out by using 10 masks.
Especially, the respective processes for forming the common electrode 75 and the conductive line 76 uses additional masks (‘mask 7’ is used for formation of the common electrode, and ‘mask 8’ is used for formation of the conductive line), whereby plural processes are carried out.
As mentioned above, the low-temperature amorphous silicon (LTPS) facilitates to realize high resolution as compared to the amorphous silicon (a-Si), and also facilitates to obtain the good TFT-operation properties. However, in comparison to using the amorphous silicon (a-Si), the increased number of mask processes causes the complicated manufacturing process, to thereby deteriorate price competition and efficiency.